Seiko LTP1245R-C384-E Manual do Utilizador Página 12

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BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series
Rev.3.0_00
Seiko Instruments Inc.
12
4. Overcharge detection voltages, overcharge detection hysteresis, overdischarge detection
voltages, overdischarge detection hysteresis, and overcurrent detection voltages (Test circuit 4)
4. 1 Overcharge detection voltages, hysteresis voltages, and overdischarge detection voltages
In the following V
MP
= V
DD
and the CDT pin is open.
The COP pin and the DOP pin should provide “Low”, which is a voltage equal to V
DD
× 0.1 V or lower, in the condition
that V1 = V2 = V3 = V4 = 3.5 V.
The overcharge detection voltage V
CU1
is defined by the voltage at which COP pin voltage becomes “High”, which is
a voltage equal to VDD × 0.9 V or higher, when the voltage V1 is gradually increased from the starting condition V1
= 3.5 V. The overcharge release voltage V
CL1
is defined by the voltage at which COP pin voltage becomes “Low”
when the voltage V1 is gradually decreased. The hysteresis voltage of the overcharge detection V
HC1
is then defined
by the difference between the overcharge detection voltage V
CU1
and the overcharge release voltage V
CL1
.
The overdischarge detection voltage V
DL1
is defined by the voltage at which DOP pin voltage becomes “High” when
the voltage V1 is gradually decreased from the starting condition V1 = 3.5 V. The overdischarge release voltage
V
DU1
is defined by the voltage at which DOP pin voltage becomes “Low” when the voltage V1 is gradually increased.
The hysteresis of the overdischarge detection voltage V
HD1
is then defined by the difference between the
overdischarge release voltage V
DU1
and the overdischarge detection voltage V
DL1
.
Other overcharge detection voltage V
CUn
, hysteresis voltage of overcharge detection V
HCn
, overdischarge detection
voltage V
DLn
, and hysteresis of the overdischarge detection voltage V
HDn
( for n = 2 to 4) are defined in the same
manner as in the case for n = 1.
4. 2 Overcurrent detection voltages
Starting condition is V1 = V2 = V3 = V4 = 3.5 V, VMP = VDD, and the CDT pin is open. The DOP pin voltage thus
provides “Low”
The overcurrent detection voltage 1, VIOV1 is defined by the voltage difference VDD VMP at which the DOP pin
voltage becomes “High” when the voltage of VMP pin is decreased.
Starting condition for measuring the overcurrent detection voltage 2 and 3 is V1 = V2 = V3 = V4 = 3.5 V, V
MP
= V
DD
and the CDT pin voltage V
CDT
= V
SS
. The DOP pin voltage thus provides “Low”.
The overcurrent detection voltage 2, V
IOV2
is defined by the voltage difference V
DD
V
MP
at which the DOP pin voltage
becomes “High” when the voltage of VMP pin is decreased.
The overcurrent detection delay time 2, t
IOV2
is a time needed for the DOP pin to become “High” from “Low” when the
VM pin voltage is changed quickly to V
IOV2
min.0.2 V from the starting condition V
MP
= V
DD
.
The overcurrent detection voltage 3, V
IOV3
is defined by the voltage of the VM pin at which the DOP pin voltage
becomes “High” when the voltage of VMP pin is decreased at the speed 10 V / ms.
The overcurrent detection delay time 3, t
IOV3
is a time needed for the DOP pin to become “High” from “Low” when the
VM pin voltage is changed quickly to V
IOV3
min.0.2 V from the starting condition V
MP
= V
DD
.
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